Effect of localized helium ion irradiation on the performance of synthetic monolayer MoS₂ field-effect transistors

• Jakub Jadwiszczak,
• Pierce Maguire,
• Conor P. Cullen,
• Georg S. Duesberg and
• Hongzhou Zhang

Beilstein J. Nanotechnol. 2020, 11, 1329–1335, doi:10.3762/bjnano.11.117

• negative gate biases [20][21]. These complex states may also improve the carrier mobility across a given gate bias range by forming stable impurity bands near the conduction band [22]. Some theoretical studies suggest, however, that individual SVs ought to act as electron acceptors in MoS2 [23][24]. As the

• . The FET channel cannot be effectively turned off in the tested bias range, with significant drain currents persisting even at Vg = −60 V. This leads to a sharp increase in the subthreshold swing and a large shift of Vth towards negative gate bias values (Δ> 10 V), thus deepening the depletion-mode n

Quantitative analysis of annealing-induced instabilities of photo-leakage current and negative-bias-illumination-stress in a-InGaZnO thin-film transistors

• Dapeng Wang and
• Mamoru Furuta

Beilstein J. Nanotechnol. 2019, 10, 1125–1130, doi:10.3762/bjnano.10.112

• recognized as an essential method to enhance the quality of the channel layer as well as its adjacent interfaces [5]. Although the initial performance of the TFTs can be improved using a passivation layer and suitable post-annealing, the devices in FPDs always undergo a negative gate bias and are exposed to

Contactless photomagnetoelectric investigations of 2D semiconductors

• Marian Nowak,
• Marcin Jesionek,
• Barbara Solecka,
• Piotr Szperlich,
• Piotr Duka and
• Anna Starczewska

Beilstein J. Nanotechnol. 2018, 9, 2741–2749, doi:10.3762/bjnano.9.256

• the frequency of the laser beam chopping. In the field effect investigations, the back-gate bias was applied using a Keithley 2410 SourceMeter instrument. The steady magnetic field induction was measured using an F.W. Bell 5080 tesla meter in the PME as well as in the Van der Pauw measurements. All

• case, the energy position of the Fermi level of graphene was modulated by the field effect through the 170 μm thick PET foil. The relative permittivity of PET is ε = 3.5 at 71 kHz [42]. Figure 6b shows the PME voltage induced in the measuring coil as a function of the back-gate bias. The inserts depict

Exploring the photoleakage current and photoinduced negative bias instability in amorphous InGaZnO thin-film transistors with various active layer thicknesses

• Dapeng Wang and
• Mamoru Furuta

Beilstein J. Nanotechnol. 2018, 9, 2573–2580, doi:10.3762/bjnano.9.239

• . Keywords: active layer thickness; gate bias; illumination stress; InGaZnO; photoleakage current; thin-film transistors; Introduction Over the last decade, the amorphous oxide-based semiconductor thin-film transistors (AOS TFTs) have attracted global attention for use in advanced display technologies due

• shift of Vth without SS degradation is well fitted to the commonly used stretched-exponential equation [28]. The obtained results suggest that electron trapping at the back-channel interface between a-IGZO and etch-stopper layers occurs because a negative gate bias is performed during NBIS. On the basis

• suggests that to improve the reliability of oxide TFTs under light irradiation and gate bias stresses, the quality of the active layer and interface engineering should be taken into account. (a) Schematic cross-sectional view and (b) the initial transfer characteristics of a-IGZO TFTs with various active

Intrinsic ultrasmall nanoscale silicon turns n-/p-type with SiO₂/Si₃N₄-coating

• Dirk König,
• Daniel Hiller,
• Noël Wilck,
• Birger Berghoff,
• Merlin Müller,
• Sangeeta Thakur,
• Giovanni Di Santo,
• Luca Petaccia,
• Joachim Mayer,
• Sean Smith and
• Joachim Knoch

Beilstein J. Nanotechnol. 2018, 9, 2255–2264, doi:10.3762/bjnano.9.210

• ultrathin Si3N4/SiO2/Si3N4: (a) physical layout shown for self-blocking p-channel FET. Schematic band diagram of such an FET shown for (b) zero and (c) negative gate bias relative to source voltage, resulting in a conductive channel by shifting the electronic Si-NWire states pinned by SiO2. Interchanging

Growth, structure and stability of sputter-deposited MoS₂ thin films

• Reinhard Kaindl,
• Bernhard C. Bayer,
• Roland Resel,
• Thomas Müller,
• Viera Skakalova,
• Gerlinde Habler,
• Rainer Abart,
• Alexey S. Cherevan,
• Dominik Eder,
• Maxime Blatter,
• Fabian Fischer,
• Jannik C. Meyer,
• Dmitry K. Polyushkin and
• Wolfgang Waldhauser

Beilstein J. Nanotechnol. 2017, 8, 1115–1126, doi:10.3762/bjnano.8.113

• semiconducting MoS2 films [43][44]. Instead, the lack of gate-bias dependence and the reasonably high conductivity independent of gate voltage, suggests metallic-like conductivity of our PVD MoS2 independent of the deposition conditions. While we do find some variation in electrical properties across samples

• (with some devices showing higher resistances, which might however be related to non-continuous film regions under the contacts), in all our measurements we find no response to the applied gate bias. Since bulk MoS2 in its most stable 2H form is a semiconductor [8] the observation of such metallic-like

Advances in the fabrication of graphene transistors on flexible substrates

• Gabriele Fisichella,
• Stella Lo Verso,
• Silvestra Di Marco,
• Vincenzo Vinciguerra,
• Emanuela Schilirò,
• Salvatore Di Franco,
• Raffaella Lo Nigro,
• Fabrizio Roccaforte,
• Amaia Zurutuza,
• Alba Centeno,
• Sebastiano Ravesi and
• Filippo Giannazzo

Beilstein J. Nanotechnol. 2017, 8, 467–474, doi:10.3762/bjnano.8.50

• determine the total electrical resistance, RTOT, between source and drain contacts are also illustrated in Figure 4d. Here, the gate-bias-dependent graphene channel resistance, Rch(Vg), the source and drain contact resistance, Rc, and the access resistance, Racc, associated with the ungated graphene access

• the scope of this paper and will be the subject of further investigations. Interestingly, working devices showed quite reproducible electrical characteristics. Figure 5a reports the output characteristics (drain current vs drain bias, Id vs Vd) at incremental values of the back gate bias (Vg from 0 to

• ) behavior, with a gradually decreasing slope (i.e., an increasing channel resistance) in the considered gate bias range. Figure 5b shows a representative transfer characteristic of the Gr-FET, i.e., Id vs Vg for a fixed drain bias (Vd = 0.1 V). It shows the typical ambipolar behavior for a graphene channel

Impact of contact resistance on the electrical properties of MoS₂ transistors at practical operating temperatures

• Filippo Giannazzo,
• Gabriele Fisichella,
• Aurora Piazza,
• Salvatore Di Franco,
• Giuseppe Greco,
• Simonpietro Agnello and
• Fabrizio Roccaforte

Beilstein J. Nanotechnol. 2017, 8, 254–263, doi:10.3762/bjnano.8.28

• (drain current, ID, vs gate bias, VG) of the device and of the on-resistance (Ron) extracted from the output characteristics (drain current, ID, vs drain bias, VDS). Clearly, all these parameters (Vth, μ, and Ron) have their own dependence on the temperature, and their combination results in the device

• Figure 3a, where the ID−VG characteristics in the gate bias range from −55 to −35 V and at different temperatures from 298 to 373 K have been reported. Such strong dependence of ID on T suggests that current transport in the subthreshold regime is dominated by thermionic current injection through the

• reverse biased source/MoS2 Schottky contact, according to the relation [5], where ΦB(VG) is the effective Schottky barrier height (SBH), modulated by the gate bias VG. To verify this, for each VG an Arrhenius plot of ID/T2 vs 1000/T is reported in Figure 3b. A nice linear dependence was observed for all

Metal oxide-graphene field-effect transistor: interface trap density extraction model

• Faraz Najam,
• Kah Cheong Lau,
• Cheng Siong Lim,
• Yun Seop Yu and
• Michael Loong Peng Tan

Beilstein J. Nanotechnol. 2016, 7, 1368–1376, doi:10.3762/bjnano.7.128

• experimental Ctot–Vgs data (from herein referred as Ctot_exp) taken from Device 1 [7], and device 2 [12] (with back-gate bias = 0 V, and Vds = 0). The extracted φs and Cit parameters obtained using experimental Ctot_exp data will be referred to as φs_exp and Cit_exp. The device parameters for both the devices

Electrical contacts to individual SWCNTs: A review

• Wei Liu,
• Christofer Hierold and
• Miroslav Haluska

Beilstein J. Nanotechnol. 2014, 5, 2202–2215, doi:10.3762/bjnano.5.229

• voltages, therefore, the transmission probability, T(E), of carriers across the SB is determined by the electric field induced by both the gate and drain–source bias. This effect is illustrated in the inset of Figure 3b, showing typical transfer characteristics of an n-type CNFET. Under a low gate bias

• more electrons to tunnel through (the n-branch shown in the inset of Figure 3b). In this regime, the current grows exponentially with an increase in the gate bias. As the gate voltage increases further, the gate-field-induced band bending effect slows down causing the source–drain current to become

•  4b). The maximum slope is obtained at a certain gate bias where the minimum current is obtained. This corresponds to the flat band condition, that is, no band bending occurs at the metal–SWCNT interface at the source electrode for this condition [36]. On the other hand, the currents measured at the

Effect of channel length on the electrical response of carbon nanotube field-effect transistors to deoxyribonucleic acid hybridization

• Hari Krishna Salila Vijayalal Mohan,
• Jianing An,
• Yani Zhang,
• Chee How Wong and
• Lianxi Zheng

Beilstein J. Nanotechnol. 2014, 5, 2081–2091, doi:10.3762/bjnano.5.217

• to consider the contribution of the change in gm, Vth and H caused by hybridization when explaining this result. Therefore, it is proper to use Δφ and K to explain the observed trend in the conductance response. Δφ and K variation with channel length Depending on the gate bias, Δφ and K can be

• gate voltage), the influence of Schottky barrier reduces, which results in lower contact resistance [35], as compared to the near-threshold regime (lower gate bias). Therefore, the contribution from the contacts to the mobility change at higher gate voltage is greater compared to lower gate voltage

Micro- and nanoscale electrical characterization of large-area graphene transferred to functional substrates

• Gabriele Fisichella,
• Salvatore Di Franco,
• Patrick Fiorenza,
• Raffaella Lo Nigro,
• Fabrizio Roccaforte,
• Cristina Tudisco,
• Guido G. Condorelli,
• Nicolò Piluso,
• Noemi Spartà,
• Stella Lo Verso,
• Corrado Accardi,
• Cristina Tringali,
• Sebastiano Ravesi and
• Filippo Giannazzo

Beilstein J. Nanotechnol. 2013, 4, 234–242, doi:10.3762/bjnano.4.24

• the back-gate bias Vg from −40 to 40 V. By linear fitting of each curve, the dependence of the specific contact resistance (ρc) and of the sheet resistance (Rsh) on the gate bias was extracted (see Figure 5c and Figure 5d, respectively). It is worth noting that both Rsh and ρc exhibit a monotonically

• increasing behaviour with the back-gate bias values in the considered bias range. Compared to the typically ambipolar behaviour observed in back-gated FET devices fabricated in graphene exfoliated from HOPG onto SiO2 (which exhibit hole conduction for negative gate bias and electron conduction for positive

• induced by the back-gate bias (Cox·Vg/q), with q being the electron charge and Cox = ε0εox/tox the oxide capacitance per unit area. By linear fitting of the experimental σ versus Vg data with Equation 2 (see insert of Figure 5d), the values of μp = 793 ± 18 cm2·V−1·s−1 and p0 = (4.4 ± 0.1) × 1012 cm−2

Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

• Farhad Larki,
• Arash Dehzangi,
• Alam Abedini,
• Ahmad Makarimi Abdullah,
• Elias Saion,
• Sabar D. Hutagalung,
• Mohd N. Hamidon and
• Jumiah Hassan

Beilstein J. Nanotechnol. 2012, 3, 817–823, doi:10.3762/bjnano.3.91

• of the channel region is in the off state at VG = 0 V, caused by the work-function difference between the gate material and the highly doped channel [2][20]. As a result, in all fabricated devices a gate bias voltage equal to the work-function difference between channel and the gate is required to

• achieve a flat-band condition. It is worth noting that the JLT is principally a gated resistor that is normally an on device at VG = 0 V [22]. When zero gate bias is applied to DGJLT, the entire channel region is neutral (i.e., not depleted), and the device is in a flat-band condition. The similar and low

Current-induced dynamics in carbon atomic contacts

• Jing-Tao Lü,
• Tue Gunst,
• Per Hedegård and
• Mads Brandbyge

Beilstein J. Nanotechnol. 2011, 2, 814–823, doi:10.3762/bjnano.2.90

• be included in the case of spin degeneracy. Based on the velocity Verlet algorithm [48] we carried out MD simulations at a varying bias voltage for zero gate bias (Vg = 0 V), and phonon friction, ηph. The MD results are summarized in Figure 6b–f. We note that for the present system setup the